1. Field of the Invention
The present invention provides a method for making a high-voltage metal-oxide-semiconductor (HVMOS) transistor, especially a high-voltage metal-oxide-semiconductor transistor with high junction breakdown voltage and decreased snap-back phenomenom.
2. Description of the Prior Art
High-voltage metal-oxide-semiconductor (HVMOS) transistors are widely used in many electrical devices, such as CPU power supplies, power management systems, AC/DC converters, etc.
Since the HVMOS transistors are commonly used under high operational voltage, the resulting high electric field leads to the incurrence of numerous hot electrons around the junction of the channel and drain. These hot electrons affect covalent electrons around the drain by causing many electron-hole pairs through the lifting of the electrons around the drain to conductive bands. Most of the ionized electrons resulting from the hot electrons move to the drain and increase the drain current I.sub.d and a small portion of the ionized electrons are injected into and become trapped in the gate oxide layer to cause a shift in gate threshold voltage. On the other hand, the holes caused by hot electrons flow to the substrate and produce a substrate current I.sub.sub. As the operational voltage increases, the quantity of electron-hole pairs correspondingly increases to lead to the phenomenon known as carrier multiplication.
Please refer to FIG. 1. FIG. 1 is cross-sectional diagram of an HVMOS transistor 30 according to the prior art. As shown in FIG. 1, the HVMOS transistor 30 is manufactured on a semiconductor wafer 10. The semiconductor wafer 10 comprises a P-type silicon substrate 11 and a P-type epitaxial layer 12 formed on the surface of the P-type silicon substrate 11. The HVMOS transistor 30 comprises a P-well region 21, an N-type source 22 formed within the P-well region 21, an N-type drain 24 formed in the P-type epitaxial layer 12, and a gate 14.
When the above-mentioned substrate current I.sub.sub flows through the silicon substrate 11, the native resistance R.sub.sub of the silicon substrate 11 itself induces an inductive voltage (V.sub.b). If the inductive voltage V.sub.b is large enough, a forward bias between the silicon substrate 11 and the source 22 will be produced and simultaneously form what is termed as a parasitic bipolar junction transistor 40. When the parasitic bipolar junction transistor 40 is turned on, current flow from the drain 24 to the source 22 abruptly increases to cause the snap-back phenomenon and produce a defective HVMOS 30. The smallest drain voltage to cause the snap-back phenomenon is termed snapback voltage. Also, the channel conductance of the HVMOS 30 of the prior art is not sufficient so that inferior current drifting occurs to easily result in the snap-back phenomenon.
However, in some HVMOS transistors, a double diffuse drain (DDD) has been extensively applied to the source/drain (S/D) structure in order to provide a higher breakdown voltage. As well, the double diffuse drain helps to suppress the hot electron effect caused by the short channel effect of the MOS transistor to further avoid electrical breakdown of the source/drain under high operational voltage. However, the above-mentioned snapback voltage degradation problem caused by the substrate current still cannot be thoroughly resolved. Therefore, importance lies in the resolution of the above-mentioned problem as well as to greatly increase the junction breakdown voltage.